1. Field of Invention
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming a triple N well.
2. Description of Related Art
As the increasing integration of a wafer, a parasitic photodiode loop is easily formed between a P-type transistor and an N-type transistor, leading to a latch-up effect and an increase of minority carrier injection into the transistor. The device performance is hence affected because of the above-mentioned phenomenon. In order to avoid the above-mentioned phenomenon, a conventional resolution is to complicate the design layout of the semiconductor devices to avoid the area which the latch-up and the minority carrier injection may occur. However, this method decreases performance of wafers. Therefore, a triple N well structure is developed to solve the above-mentioned problems and to simplify the design layout of the semiconductor devices.
FIG. 1 is a schematic, cross-sectional view showing a conventional triple N well structure. As shown in FIG. 1, a cell well 112 of P type is embedded in a substrate 100. The cell well 112 is surrounded by an annular shallow N well 110. From the cross-sectional view, the annular shallow N well 110 lies beside the cell well 112. A deep N well 108 lies below the cell well 12 and the annular shallow N well 110. Therefore, from the cross-sectional view, the cell well 112 is surrounded with a triple N well composed of the annular shallow N well 110 and the deep N well 108. Commonly, an N type transistor (not shown) is formed on the cell well 112. Additionally, an N well 113 adjacent to the triple well is formed in the substrate 100. Typically, a P type transistor (not shown) is formed on the N well 113.
The above-mentioned triple N well can efficiently isolate the transistor on the cell well from other devices on the other N well to avoid occurrence of minority carrier injection and mutual disturbance between these devices and to simplify the design layout of the semiconductor devices.
Accordingly, the invention provides a method of forming a triple N well. The method needs only two masks to form a triple N well. Thus manufacturing time and cost can be greatly reduced and the same insulating effect can be obtained as a conventional method.
As embodied and broadly described herein, the invention provides a method of forming a triple N well. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. A fourth ion implantation step is performed to form a cell well surrounded by the triple N well. The cell well lies above the transversal deep N well. The second mask layer is removed.
Accordingly, the invention provides a method of forming a semiconductor device. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well and a retrograde barrier well in the substrate. A second ion implantation step is performed to form an annular longitudinal shallow N well and an N well in the substrate. The annular longitudinal shallow N well lies above the annular longitudinal deep N well. The N well lies above the retrograde barrier well. The first mask layer is removed. A second patterned mask layer is formed on the substrate. A third ion implantation step is performed to form a transversal deep N well surrounded by the annular longitudinal deep N well. The transversal deep N well is connected with the annular longitudinal deep N well. A fourth ion implantation step is performed to form a cell well surrounded by the triple N well. The cell well lies above the transversal deep N well. The second mask layer is removed.
The invention can use the same mask to continuously perform ion implantation steps by controlling dosage and energy of dopants so as to form a N type well or a P type well with different depths in the substrate. The invention needs only two mask layers, thus, manufacturing time and cost can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.